Many different types and styles of memory exist to store data for computers and similar type systems. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory are all presently available to accommodate data storage.
Flash NOR memory is generally constructed of many memory cells where, generally, single bits of data are stored in and read from respective memory cells. The cells are generally programmed by hot electron injection and erased by Fowler-Nordheim tunneling or hot hole injection, however other mechanisms of programming and/or erasing can be employed.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the memory cell. In an erase or write operation the voltages are applied so as to cause a charge to be removed or stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to How in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed.
The memory cell generally has a source, a drain, and a channel formed there between, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
In a NOR configuration, the control gate is connected to a wordline associated with a row of memory cells to form sectors of such cells. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. Respective drain terminals of the transistors within a single column are connected to the same bitline. In addition, respective flash cells associated with a given bitline have slacked gate terminals coupled to a different wordline, while all the flash memory cells in the array generally have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using the peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
By way of further detail, the single bit stacked gate flash memory cell is programmed by a suitable mechanism, such as hot electron injection. Programming with hot electron injection involves applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. When a resulting electric field is high enough, electrons collect enough energy to be injected from the source onto the control gate. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit slacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
For a read operation, a certain voltage bias is applied across the drain to source of the cell transistor. The drain of the cell is the bitline, which may be connected to the drains of other cells in a byte or word group. A source read voltage is applied at the source and a drain read voltage is applied at the drain. The drain read voltage is greater than the source read voltage. A read gate voltage is then applied to the gate (e.g., the wordline) of the memory cell transistor that is greater than the drain read voltage in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed threshold voltage (Vt) and an unprogrammed threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
Another type of flash memory is dual bit memory, which allows multiple bits to be stored in a single cell. In this technology, a memory cell is essentially split into two identical, complementary parts, each of which is formulated for storing one of two independent bits. Each dual bit memory cell, like a traditional cell, has a gate with a source and a drain. However, unlike a traditional slacked gate cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, respective dual bit memory cells can have the connections of the source and drain reversed during operation to permit the storing of two bits.
In a virtual ground type architecture, dual bit memory cells have a semiconductor substrate with conductive bitlines. A multilayer storage layer, referred to as a “charge-trapping dielectric layer”, is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a first insulating layer, a charge-trapping layer, and a second insulating layer. Wordlines are formed over the charge-trapping dielectric layer substantially perpendicular to the bitlines. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts us a control gate, and changing bitline connections such that one bit is stored by the source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being connected in another arrangement.
In a NAND type architecture, individual memory cell (which single bit stacked gate, or dual bit memory cells) are arranged in a serially-coupled string, with select transistor devices on top and bottom portions of the serial string that form a bit line. Each cell gate terminal is coupled to a unique word line. By appropriate addressing of the various word lines, individual memory cells along the serial string may be addressed.
In each of the various architectures highlighted above, each bit of the memory cell may be one of two distinct states, for example, a “0” or a “1” state. These types of memory cells are often referred to a single level cells (SLC), wherein the state of the cell may be ascertained by comparing the cell data to a reference cell having a single state that resides somewhere between the two distinct data states. By comparing the current in the programmed cell to a reference current of a reference data cell, the state of the bit at issue may be determined.
Another conventional form of non-volatile memory that use the above stacked gate or dual bit device structures is often referred to as a multi-level cell (MLC). In a multi-level memory cell a single physically distinct data bit may have more than two distinct states. For example, one type of common multi-level memory cell is referred to as a quad bit cell since each physical bit may be one of four distinct data states. Therefore in a conventional stacked gate type memory structure, the single bit may be one of multiple data states greater than two. Similarly, in a dual bit type memory structure, each of the two physically distinct data bits may be one of multiple data states. Such memory cells are often referred to as a multi-level cell. In order to ascertain the data state of each physically distinct bit, the current associated therewith is compared with multiple reference currents associated with multiple reference data cells.